Electronic Products Inc. (EPI) is a powder to package, fully integrated HTCC technical ceramics and glass-to-metal package manufacturer. The following information details our ceramic packaging capabilities and offers design guidelines. View our facility page to learn more about our vertically integrated process capabilities.
We specialize in multiple ceramics including:We can accept a simple print and most software formats for your prototype design. We are using Solidworks, DraftSight, Sonnet EM, ANSYS DesignSpace and CST Microwave Studio.
Below is a general overview of our multilayer ceramic process using an example design. Each device is manufactured using it's own process with our extensive in-house equipment capabilities for maximum efficiency. For more information on our vertically integrated process capabilities click here.
Standard | Custom | |
---|---|---|
1. Max Size (A x B): | 2 x 2 [50.8 x 50.8] | 3 x 3 [76.2 x 76.2] |
2. Tolerance (As fired)
|
±1%, NLT ±.005 [0.127] ±10%, NLT ±.002 [0.051] 0.004/inch [.102/mm] |
±0.5%, NLT ±.003 [0.076] ±7%, NLT ±.002* [0.051] 0.003/inch [.76/mm] |
3. Number of Layers (C):
|
2 0.010 to 0.060 [0.250 to 1.50] Typ. |
10 Up to 0.150 [4.00] |
4. Cavity Depth | 0.040 [1.00] Typ. | Upto 0.120 [3.00] |
Standard ° | Custom | |
---|---|---|
A. Via Hole Diameter: | .010 [0.254] | .006 [0.152] |
B. Via Cover Dot Diameter: | .020 [0.508] | .012 [0.305] |
C. Via Center Spacing: | 3 x Θ | 3 x Θ |
D. Via Center Spacing: | 3 x Θ | 3 x Θ |
E. Via Center Spacing: | 3 x Θ | 3 x Θ |
F. Via Cover Dot to Line Clearance: | .012 [0.305] | .008 [0.203] |
G. Line Width: | .010 [0.254] | .005 [0.127] |
H. Line to Line Clearance: | .010 [0.254] | .006 [0.152] |
I. Line Center Spacing; | .020 [0.508] | .008 [0.203] |
J. Cavity to Via Center: | 3 x Θ | 2.5 x Θ |
K. Outside Edge to Via Center: | 4 x Θ | 3 x Θ |
L. Line to Outside Edge: | .020 [0.508] | .015 [0.381] |
Standard ° | Custom | |
---|---|---|
A. Closed Hole Diameter: | .020 [0.508] | .015 [0.381] |
B. Via Cover Dot Diameter: | .020 [0.508] | .014 [0.356] |
C. Open Hole Diameter: | .020 [0.508] | .015 [0.381] |
D. Via Cover Dot Diameter: | .020 [0.508] | .014 [0.356] |
E. Opening Diameter: | .020 [0.508] | .015 [0.381] |
F. Castellation (Chip Carrier): | Θ.020 [0.254] | Θ.015 [0.381] |
G. Castellation (Chip Carrier): | Θ.020 [0.254] | Θ.015 [0.381] |
H. Solid Via Diameter: | Θ.006 - 0.15 [0.152 - 0.381] Typ. |
92% Alumina (Al2O3) | 94% Alumina (Al2O3) | 99.8% Alumina (Al2O3) | Zirconia Toughened Alumina (ZTA) | Aluminum Nitride(AlN) | |
---|---|---|---|---|---|
Color: | Black | White | White | White | Gray |
Crystal Size (µm): | 8 | 8 | 8 | 6 | 5 |
Water Absorption (%): | 0 | 0 | 0 | 0 | 0 |
Density (g/cc): | 3.67 | 3.67 | 3.91 | 4.3 | 3.3 |
Hardness (V): | 12 | 13 | 15 | 14.5 | 11.5 |
Fracture Toughness (MPam^0.5): | 3~4 | 4~5 | 3~4 | 6 | 3 |
Flexural Strength (MPa): | 630 | 430 | 450 | 640 | 290 |
Modulus (GPa): | 320 | 320 | 380 | 338 | 330 |
Compressive Strength (MPa): | 1800 | 2200 | 2300 | 2800 | 2100 |
CTE (x10^-6/°C): | 7 | 7 | 6.5 | 6 | 4.5 |
Thermal Conductivity @25°C (W/mK): | 20 | 25 | 30 | 25 | 180 |
Specific Heat (J/gK): | 0.79 | 0.78 | 0.79 | - | 0.72 |
Dielectric Strength (KV/mm): | 12 | 16 | 16 | 14 | 16 |
Dielectric Constant (@ 1MHz): | 10 | 9.5 | 10 | 12.4 | 8.5 |
Dielectric Constant (@ 1GHz): | 10 | 9.5 | 9.6 | 9.5 | 8.4 |
Dielectric Loss (@ 1MHz): | 0.0013 | 0.003 | 0.001 | 0.005 | 0.005 |
Volume Resistivity: | >10^14 | 10^14 | 10^14 | 10^14 | 10^14 |
Tungsten | |
---|---|
Bulk Modulus (GPa): | 310 |
Shear Modulus (GPa): | 161 |
Melting Point: | 3410°C ±30ºC |
Boiling Point: | 5500ºC |
CTE (x10^-6/°C): | 4.5 |
Adhesion: | 4.3K g/mm^2 (6,000 psi) |
Solder Leach: | 10 Cycles - No Degradation of Nickel Over Tungsten (30 Seconds Dipping Per Cycle in 60/40 @ 230°C) |
Thermal Conductivity @25°C (W/mK): | 150-160 |
Electrical Resistivity: | 5.5 x 10-8OΩ per cm |
External Sheet Resistivity (plated): | 5mΩ/square |
Internal Sheet Resistivity: | 10mΩ-12mΩ/square |